1. Field of the Invention
This invention relates to a clock switching circuit for switching the internal clock for an interface having a hot-plug function such as IEEE1394 or USB, and more particularly to a clock switching circuit that prevents the occurrence of hazards during switching, makes it possible to generate a stable clock, and prevents malfunction of the internal circuits.
2. Related Art
Recent personal computers perform the connection with peripheral devices by an interface having a hot-plug function. A hot-plug function is a function that activates the connection even when an interface cable is connected after the power to the computer and peripheral device have been turned ON. For example, when an interface cable having a hot-plug function is connected to the device to be connected after the personal computer has started up, the connection with that connected device is activated, and when the interface cable is disconnected, the connection with the connected device is deactivated.
When the connection is activated, the internal circuits of the connected device are also activated, and specified high-speed processes, that are controlled by the synchronization clock, are executed. Moreover, after the cable has been disconnected, the connection is deactivated and the internal circuits of the connected device are also deactivated. However, internal circuits continue a minimum of operations for a preparation of the cable connection later.
The aforementioned IEEE1394 interface having a hot-plug function has a high-speed transmission rate of 400 Mbps, and is a suitable interface for transmitting image data. In order to correspond with this interface, the connected device has a PLL circuit which speeds up the oscillating clock of the internal oscillator. Moreover, it is desired that while the connected device is activated, the internal circuits perform a predetermined operation in synchronization with the high-speed clock of the PLL circuit, and while the connected device is not activated, the internal circuits maintain a minimum operation in synchronization with the oscillation clock of the low-speed oscillator.
Therefore, it is necessary for the internal circuits of the connected device to switch between the high-speed clock and the low-speed clock in response to the connection or disconnection of the interface cable. In this case, it is necessary to switch between two clocks that are asynchronous and out of phase with each other. In prior clock switching circuits, it is not possible to adequately prevent the occurrence of hazards when switching.
FIG. 1 is a circuit diagram of a prior clock switching circuit. This clock switching circuit is as disclosed in Japanese Laid-open Patent No. H01-6209309, and is used for switching asynchronous clocks in communication devices. With the switching circuit in FIG. 1, switching is performed by a selection signal ‘Select’ that selects between the output clock X'tal of a quartz oscillator or the output clock PLL of a PLL circuit. In order to prevent hazards, which are the cause of malfunction when switching between the asynchronous clocks X'tal and PLL, the quartz oscillator clock side comprises flip-flops F/F(1), F/F(2) and an AND gate AND1, and switching is performed in synchronization with the clock X'tal, while the PLL side also comprises flip-flops F/F(3), F/F(4) and an AND gate AND2, and switching is performed in synchronization with the clock PLL.
FIG. 2 is a timing chart of the operation of the clock switching circuit shown in FIG. 1. The selection signal ‘Select’ is HI-level when the interface cable is disconnected, and is LO-level when the interface cable is connected. FIG. 2 shows the operation when the interface cable changes from being connected to being disconnected, as well as the operation when returning to the connected state.
As shown in FIG. 2, when the selection signal ‘Select’ is in the LO-level connection state, the clock output COUT of the switching circuit outputs the high-speed clock PLL of the PLL circuit. At that point, when the cable is disconnected and the selection signal ‘Select’ becomes HI-level, then in response to the fall of the clock X'tal at time t1, the flip-flop F/F(1) receives the HI-level of the selection signal ‘Select’. Then, at time t2, in response to the fall of the clock PLL, the flip-flops F/F(3), (4) receive the inverted signal (LO level) of the selection signal ‘Select’. In this way, the AND gate AND2 prohibits the output of the clock PLL, and the clock output COUT stops. Furthermore, in response to the fall of the clock X'tal at time t3, the flip-flop F/F(2) transfers the selection signal ‘Select’, and the AND gate AND1 lets the clock X'tal pass. As a result, the clock output COUT is switched to the quartz oscillator clock X'tal.
In response to the selection signal ‘Select’ being switched as described above, the deactivated clock is disconnected by one clock operation, and the activated clock is activated by 2 clock operations, and therefore the occurrence of hazards during switching is prevented. Furthermore, the activated clock is activated in synchronization with that clock phase, so there is no occurrence of a hazard that causes malfunction.
FIG. 3 is a different operation timing chart of the clock switching circuit in FIG. 1. In this case, the clock PLL may operate at very high-speed when compared with the clock X'tal. In this example, the frequency of the clock PLL is two times the frequency of the quartz clock X'tal. The HI level of the selection signal ‘Select’ is received by the flip-flops F/F(3), (4) at time t11, which prohibits output of the high-speed clock PLL, and at time t12, the HI level of the selection signal ‘Select’ is received by the flip-flop F/F(1), and at the trailing edge of the quartz clock X'tal at time t13, the output of the flip-flop F/F(1) is received by the next stage flip-flop F/F(2), and the AND gate AND1 is opened and the low-speed quartz clock X'tal is output to the output clock COUT.
When the interface cable is connected, the selection signal ‘Select’ becomes LO-level. This state is received by the flip-flop F/F(3) at time t14, and then received by the next stage flip-flop F/F(4) at the next trailing edge at time t15. However, as described above, since the quartz clock X'tal is half or less the frequency of the high-speed flip-flop PLL, at time t16 after time t15, the flip-flops F/F(1), (2) receive the LO-level selection signal ‘Select’ when the clock X'tal first falls, and the output of the low-speed quartz clock X'tal is prohibited. However, at the switching inside the circle in the figure, a hazard may occur in the output clock COUT.
The IEEE1394 interface operates at 400 Mbps and is a very high-speed interface, so there is a possibility that the relationship between the PLL circuit clock and the quartz clock may become as shown in FIG. 3. In that case, with the prior clock switching circuit in FIG. 1, there is a possibility that malfunction will occur in the logical circuits in the later stages to which the output clock COUT is supplied.
Furthermore, when the interface cable is connected, the clock is switched from the low-speed quartz clock to the high-speed PLL clock, however, when the PLL circuit that starts operating after switched is unstable after switching, then an unstable clock will be supplied to the later stage circuits and malfunction will occur.